Why Signal and Power Integrity
Digital signal frequencies used on PCBs continue to rise. Now bit rates on fast serial interfaces are passing 20Gbps/lane (e.g., DP2.0, USB4). This is clearly a speed when a high-speed digital interface design becomes RF design.
Signal integrity (SI) – Check and improve performance of your high-speed PCB
We use advanced 3D EM simulation tools to improve critical portions of the high-speed lane routing, such as vias, component, and connector areas. The designer gets information on impedances of the routing at different locations and S-param models showing the frequency response of the transmission path from the simulation. S-param model allows tuning of equalization for the path when available. We also run lower frequency (<< 5GHz) analysis showing signal waveforms used to tune driver strengths and terminations. This is often the case with fast clock signals and memory interfaces (e.g., SC cards and DRAMs).
Power Integrity (PI)
With power integrity analysis, power delivery network (PDN) performance is checked both for AC and DC. DC analysis ensures that enough DC power can be delivered without voltage drops and too high current densities improving also reliability. AC impedance of PDN is analyzed to meet specifications given for high performance and high current IC’s. The target here is to secure power delivery also at higher frequencies. This improves EMI levels of the processor subsystem as well.
- S-param and TDR analysis of fast interfaces, over 20Gbps/lane, supported
- Signal waveform analysis (SI)
- AC and DC PDN analysis (PI)